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HANBit
HMD8M32M16EG
32Mbyte(8Mx32) 72-pin EDO MODE 2K Ref. SIMM Design 5V Part No. HMD8M32M16EG
GENERAL DESCRIPTION
The HMD8M32M16EG is a 8M x 32bit dynamic RAM high density memory module. The module consists of sixteen CMOS 4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
w Part Identification HMD8M32M16EG- 2048 Cycles/32ms Ref. Gold w Access times : 50, 60ns w High-density 32MByte design w Single + 5V 0.5V power supply w JEDEC standard PDpin and pinout w EDO mode operation w TTL compatible inputs and outputs w FR4-PCB design PIN 1 2 3 4 5 6 7 8 9
PIN ASSIGNMENT
SYMBOL Vss DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBOL DQ22 DQ7 DQ23 A7 NC Vcc A8 A9 NC NC NC NC NC NC Vss /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 NC /WE NC SIMM tRC 90ns 110ns tHPC 26ns 30ns TOP VIEW
Note: A11 is not used for HMD8M32M16EG
PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
SYMBOL DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 Vcc DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC Vss
OPTIONS
w Timing 50ns access 60ns access w Packages 72-pin SIMM
MARKING
-5 -6 M
10 11 12 13 14 15 16 17 18 60ns NC Vss NC NC 19 20 21 22 23 24
PRESENCE DETECT PINS
Pin PD1 PD2 PD3 PD4 50ns NC Vss Vss Vss
PERFORMANCE RANGE
Speed 5 6 tRAC 50ns 60ns tCAC 13ns 15ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
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HMD8M32M16EG
FUNCTIONAL BLOCK DIAGRAM
/CAS0
/RAS0
/CAS DQ1 /RAS DQ2 U2 /OE DQ3 /W A0 -A10(A11) DQ4
DQ0-3
DQ1 /CAS DQ2 /RAS U11 DQ3 /OE DQ4 A0-A10(A11) /W
/RAS1
/CAS DQ1 /RAS DQ2 U4 /OE DQ3 /W A0 -A10(A11) . DQ4
/CAS1
DQ4-7
DQ1 /CAS DQ2 /RAS U13 DQ3 /OE DQ4 A0-A10(A11) /W
/CAS U6 /RAS /OE /W A0 -A10(A11).
DQ1 DQ2 DQ3 DQ4
DQ8-11
DQ1 /CAS U15 DQ2 /RAS DQ3 /OE DQ4 A0-A10(A11) /W
/CAS /RAS U8 /OE /W A0 -A10(A11).
/CAS2
DQ1 DQ2 DQ3 DQ4
DQ12-15
DQ1 /CAS DQ2 /RAS U17 DQ3 /OE DQ4 A0-A10(A11) /W
/CAS U3 /RAS /OE /W A0 -A10(A11).
DQ1 DQ2 DQ3 DQ4
DQ16-19
DQ1 /CAS U12 DQ2 /RAS DQ3 /OE DQ4 A0-A10(A11) /W
/CAS /RAS U5 /OE /W A0 -A10(A11).
/CAS3
DQ1 DQ2 DQ3 DQ4
DQ20-23
DQ1 /CAS DQ2 /RAS U14 DQ3 /OE DQ4 A0-A10(A11) /W
/CAS DQ1 U7 /RAS DQ2 /OE DQ3 /W A0 -A10(A11) DQ4
DQ24-27
DQ1 /CAS U16 DQ2 /RAS DQ3 /OE DQ4 A0-A10(A11) /W
/CAS U9 /RAS /OE /W A0 -A10(A11).
/WE A0-A10 (A11)
DQ1 DQ2 DQ3 DQ4
DQ28-31
DQ1 /CAS U18 DQ2 /RAS DQ3 /OE DQ4 A0-A10(A11) /W
URL:www.hbe.co.kr REV.1.0 (August.2002)
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ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD8M32M16EG
RATING -1V to 7.0V -1V to 7.0V 16W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS ( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP. 5.0 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS SYMBOL ICC1 -6 ICC2 ICC3 -6 -5 ICC4 -6 ICC5 ICC6 -6 Il(L) IO(L) VOH VOL ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=VIH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min )
URL:www.hbe.co.kr REV.1.0 (August.2002) HANBit Electronics Co.,Ltd.
SPEED -5
MIN -80 -10 2.4 -
MAX 816 736 32 816 736 896 816 16 816 736 80 10 0.4
UNITS Ma MA MA MA MA MA MA MA MA MA A A V V
Don't care -5
Don't care -5
ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.)
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ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min )
HMD8M32M16EG
IIL : Input Leakage Current (Any input 0V VIN 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
o
CAPACITANCE
( TA=25 C, Vcc = 5V, f = 1Mz ) DESCRIPTION SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1 MIN MAX 100 130 40 30 20 UNITS pF pF pF pF pF
Input Capacitance (A0-A11) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
AC CHARACTERISTICS
( 0 C TA 70oC , Vcc = 5V10%, See notes 1,2.) -5 -6 UNIT MIN MAX MIN 110 50 13 25 3 3 2 30 50 13 38 8 20 15 5 0 10 0 10K 37 25 10K 13 50 3 3 2 40 60 15 45 10 20 15 5 0 10 0 10K 45 30 10K 13 50 60 15 30 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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o
STANDARD OPERATION Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time
URL:www.hbe.co.kr REV.1.0 (August.2002)
SYMBOL tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC 90
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Column address hold time Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command hold referenced to /RAS Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge to /CAS hold time Access time from /CAS precharge /CAS precharge time (Fast page) /RAS pulse width (Fast page ) /W to /RAS precharge time (C-B-R refresh) /W to /RAS hold time (C-B-R refresh) NOTES tWRH 10 tCAH tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCPA tCP tRASP tWRP 8 50 10 200K 0 5 10 5 30 8 25 0 0 0 10 50 10 13 8 0 8 32
HMD8M32M16EG
10 30 0 0 0 10 55 10 10 10 0 10 32 0 5 10 5 35 10 60 10 200K ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10
ns
1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles.
URL:www.hbe.co.kr REV.1.0 (August.2002) HANBit Electronics Co.,Ltd.
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HMD8M32M16EG
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE
/RAS
VIHVILtCRP tRCD tRAD tASR tRAH tASC
tRC tRAS tCSH tRSH tCAS tCAH
COLUMN ADDRESS
tRP
tCRP
/CAS
VIHVIL-
tRAL
A
VIHVILROW ADDRESS
tRCS /W VIHVIL/OE VIHVILDQ0-DQ7 VOHVOLOPEN
tRRH tAA tOEA tCAC tCLZ tREZ
tRCH tWEZ tCEZ
tOEZ
tRAC
DATA-OUT
TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE) NOTE : Dout = Open
tRC tRAS tCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
VIH/RAS VIL-
tRP
tCSH
tRSH tCAS tRAL
tCRP
VIH/CAS VILVIHA VILROW ADDRESS
tCWL tRWL tWCS tWCH tWP
VIH/W VILVIHVILtDS DQ0-DQ7 VOHVOLURL:www.hbe.co.kr REV.1.0 (August.2002) DATA-IN HANBit Electronics Co.,Ltd.
/OE
tDH
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PACKAGING INFORMATION
SIMM Design
HMD8M32M16EG
108.0 mm 3.38 mm R 1.57 mm 101.19 mm 3.18 mm DIA 0.51 mm
21.50 10.16 mm 6.35 mm
1
72
2.03 mm 1.02 mm 6.35 mm 95.25 mm 6.35 mm 1.27 3.34 mm
0.25 mm MAX
2.54 mm MIN
1.29 0.08mm
Gold : 1.040.10 mm 1.27 Solder:0.9140.10mm
ORDERING INFORMATION
Component Number 16EA 16EA
Part Number
Density
Org.
Package
Vcc
Access Time
HMD8M32M16EG-5 HMD8M32M16EG-6
32MByte 32MByte
8MX 32bit 8MX 32bit
72Pin-SIMM 72Pin-SIMM
5V 5V
50ns 60ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
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